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FUJITSU SEMICONDUCTOR DATA SHEET
ADVANCED INFO.
AE0.1E
MEMORY
CMOS
4 x 512 K x 32 BIT SYNCHRONOUS DYNAMIC RAM
MB81F643242C-60/-70/-10
CMOS 4-Bank x 524,288-Word x 32 Bit Synchronous Dynamic Random Access Memory s DESCRIPTION
The Fujitsu MB81F643242C is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing 67,108,864 memory cells accessible in a 32-bit format. The MB81F643242C features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81F643242C SDRAM is designed to reduce the complexity of using a standard dynamic RAM (DRAM) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a conventional DRAM. The MB81F643242C is ideally suited for workstations, personal computers, laser printers, high resolution graphic adapters/accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed.
s PRODUCT LINE & FEATURES
Parameter CL - tRCD - tRP Clock Frequency Burst Mode Cycle Time Access Time from Clock CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 MB81F643242C -60 2 - 2 - 2 clk min. 3 - 3 - 3 clk min. 167 MHz max. 10 ns min. 6 ns min. 6 ns max. 5.5 ns max. 165 mA max. -70 -10 2 - 2 - 2 clk min. 2 - 2 - 2 clk min. 3 - 3 - 3 clk min. 3 - 3 - 3 clk min. 143 MHz max. 100 MHz max. 10 ns min. 15 ns min. 7 ns min. 10 ns min. 6 ns max. 7 ns max. 5.5 ns max. 7 ns max. 155 mA max. 115 mA max. 2 mA max. 2 mA max. Reference Value@ 67 MHz, CL=3 2 - 2 - 2 clk min. 3 - 3 - 3 clk min. 67 MHz max. 20 ns min. 15 ns min. 7 ns max. 7 ns max. 100 mA max.
Operating Current Power Down Mode Current (ICC2P) Self Refresh Current (ICC6) * * * * *
Single +3.3 V Supply 0.3 V tolerance LVTTL compatible I/O interface 4 K refresh cycles every 64 ms Four bank operation Burst read/write operation and burst read/single write operation capability
* Programmable burst type, burst length, and CAS latency * Auto-and Self-refresh (every 15.6 s) * CKE power down mode * Output Enable and Input Data Mask
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s PACKAGE
86 pin Plastic TSOP(II) Package
(FPT-86P-M01) (Normal Bend)
Package and Ordering Information
- 86-pin plastic (10.16 x 22.22 mm) TSOP-II without SCITT Function, order as MB81F643242C-xxFN - 86-pin plastic (10.16 x 22.22 mm) TSOP-II with SCITT Function, order as MB81F643242C-xxFN-S
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s PIN ASSIGNMENTS AND DESCRIPTIONS
86-Pin TSOP(II) (TOP VIEW)
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 N.C. VCC DQM0 WE CAS RAS CS N.C. BA0 BA1 A10/AP A0 A1 A2 DQM2 VCC N.C. DQ16 VSSQ DQ17 DQ18 VCCQ DQ19 DQ20 VSSQ DQ21 DQ22 VCCQ DQ23 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 N.C. VSS DQM1 N.C. N.C. CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS N.C. DQ31 VCCQ DQ30 DQ29 VSSQ DQ28 DQ27 VCCQ DQ26 DQ25 VSSQ DQ24 VSS
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Pin Number 1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86 14, 21, 30, 57, 69, 70, 73 17 18 19 20 22, 23 24 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 67 68 16, 28, 59, 71
Symbol VCC, VCCQ DQ0 to DQ31 VSS, VSSQ N.C. WE CAS RAS CS BA1, BA0 AP A0 to A10 CKE CLK DQM0 to DQM3 Supply Voltage Data I/O Ground No Connection Write Enable
Function
Column Address Strobe Row Address Strobe Chip Select Bank Select (Bank Address) Auto Precharge Enable Address Input Clock Enable Clock Input Input Mask/Output Enable * Row: A0 to A10 * Column: A0 to A7
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s BLOCK DIAGRAM
Fig. 1 - MB81F643242C BLOCK DIAGRAM
CLK
To each block
CLOCK BUFFER
CKE
BANK-3 BANK-2 BANK-1 BANK-0 RAS
CS
CONTROL SIGNAL LATCH COMMAND DECODER
CAS
RAS
CAS
WE
WE
MODE REGISTER
A0 to A9, A10/AP
DRAM CORE (2,048 x 256 x 32)
ADDRESS BUFFER/ REGISTER
BA1 BA0
ROW ADDR.
DQM0 to DQM3
COLUMN ADDRESS COUNTER I/O DATA BUFFER/ REGISTER
COL. ADDR. I/O
VCC VCCQ VSS VSSQ
DQ0 to DQ31
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s FUNCTIONAL TRUTH TABLE Note *1
COMMAND TRUTH TABLE
Function Device Deselect No Operation Burst Stop Read Read with Auto-precharge Write Write with Auto-precharge Bank Active Precharge Single Bank Precharge All Banks Mode Register Set Notes: *1. *2. *3. *4. *5. *6. *8, *9 *6
Note *2, *3, and *4
CKE CS n-1 *5 *5 DESL NOP BST READ H H H H H H H H H H H n X X X X X X X X X X X H L L L L L L L L L L X H H H H H H L L L L X H H L L L L H H H L X H L H H L L H L L L RAS CAS WE BA1, A10 BA0 (AP) X X X V V V V V V X L X X X L H L H V L H L A9 to A8 X X X X X X X V X X V A7 to A0 X X X V V V V V X X V
Notes Symbol
*6 READA *6 WRIT
*6 WRITA *7 ACTV PRE PALL MRS
*7. *8. *9.
V = Valid, L = Logic Low, H = Logic High, X = either L or H. All commands assumes no CSUS command on previous rising edge of clock. All commands are assumed to be valid state transitions. All inputs are latched on the rising edge of clock. NOP and DESL commands have the same effect on the part. Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions. READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has been activated (ACTV command). Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION". ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL command). Required after power up. MRS command should only be issued after all banks have been precharged (PRE or PALL command). Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION".
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
DQM TRUTH TABLE
CKE Function Data Write/Output Enable Data Mask/Output Disable Symbol n-1 ENBi *1 MASKi *1 H H n X X DQMi *1, *2 L H
Notes: *1. i = 0, 1, 2, 3 *2. DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31,
CKE TRUTH TABLE
Current State Bank Active CKE Function Clock Suspend Mode Entry Notes Symbol n-1 *1 CSUS *1 H L L *2 *2, *3 REF SELF H H L Self Refresh Self-refresh Exit *4 SELFX L H Idle Power Down Entry *3 PD H L Power Down Power Down Exit L H H X X X X X X L H H L X H X H X H X X X X X X H L H L X H X H X H X X X X X X n L L H H L H A10 CS RAS CAS WE BA1, (AP) BA0 X X X L L L X X X L L H X X X L L H X X X H H H X X X X X X X X X X X X A9 to A0 X X X X X X
Any Clock Suspend Continue (Except Idle) Clock Suspend Idle Idle Clock Suspend Mode Exit Auto-refresh Command Self-refresh Entry
Notes: *1. The CSUS command requires that at least one bank is active. Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION". NOP or DSEL commands should only be issued after CSUS and PRE(or PALL) commands asserted at the same time. *2. REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL command). Refer to "STATE DIAGRAM" in section "s FUNCTIONAL DESCRIPTION". *3. SELF and PD commands should only be issued after the last read data have been appeared on DQ. *4. CKE should be held high within one tRC period after tCKSP.
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
OPERATION COMMAND TABLE (Applicable to single bank)
Current State Idle CS H L L L L L L L L Bank Active H L L L L L L L L RAS CAS WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Addr X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS NOP NOP NOP Illegal Illegal Bank Active after tRCD NOP Auto-refresh or Self-refresh Mode Register Set (Idle after tRSC) NOP NOP NOP Begin Read; Determine AP Begin Write; Determine AP Illegal *2 *3, *6 *3, *7 *2 *2 Function Notes
Precharge; Determine Precharge Type Illegal Illegal
(Continued)
8
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current State Read CS H RAS CAS WE X X X Addr X Command DESL Function Notes
NOP (Continue Burst to End Bank Active) NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, New Read; Determine AP Terminate Burst, Start Write; Determine AP Illegal Terminate Burst, Precharge Idle; Determine Precharge Type Illegal Illegal NOP (Continue Burst to End Bank Active) NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, Start Read; Determine AP Terminate Burst, New Write; Determine AP Illegal Terminate Burst, Precharge; Determine Precharge Type Illegal Illegal *2 *4 *4 *2
L L L
H H H
H H L
H L H
X X BA, CA, AP
NOP BST READ/READA
L L L L L Write H
H L L L L X
L H H L L X
L H L H L X
BA, CA, AP BA, RA BA, AP X MODE X
WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL
L L L
H H H
H H L
H L H
X X BA, CA, AP
NOP BST READ/READA
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, AP BA, RA BA, AP X MODE
WRIT/WRITA ACTV PRE/PALL REF/SELF MRS
(Continued)
9
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current State Read with Autoprecharge CS H RAS CAS WE X X X Addr X Command DESL Function NOP (Continue Burst to End Precharge Idle) NOP (Continue Burst to End Precharge Idle) Illegal Illegal Illegal Illegal Illegal Illegal Illegal NOP (Continue Burst to End Precharge Idle) NOP (Continue Burst to End Precharge Idle) Illegal Illegal Illegal Illegal Illegal Illegal Illegal *2 *2 *2 *2 *2 *2 *2 *2 Notes
L L L L L L L L Write with Autoprecharge H
H H H H L L L L X
H H L L H H L L X
H L H L H L H L X
X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X
NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL
L L L L L L L L
H H H H L L L L
H H L L H H L L
H L H L H L H L
X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE
NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS
(Continued)
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current State Precharging CS H L L L L L L L L Bank Activating H L L L L L L L L RAS CAS WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Addr X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS Function NOP (Idle after tRP) NOP (Idle after tRP) NOP (Idle after tRP) Illegal Illegal Illegal NOP (PALL may affect other bank) Illegal Illegal NOP (Bank Active after tRCD) NOP (Bank Active after tRCD) NOP (Bank Active after tRCD) Illegal Illegal Illegal Illegal Illegal Illegal *2 *2 *2 *2 *2 *2 *2 *5 Notes
(Continued)
11
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current State Refreshing CS H L L RAS X H H CAS X H L WE X X X Addr X X X Command DESL NOP/BST Function NOP (Idle after tRC) NOP (Idle after tRC) Notes
READ/READA/ Illegal WRIT/WRITA ACTV/ PRE/PALL REF/SELF/ MRS DESL NOP BST Illegal
L
L
H
X
X
L Mode Register Setting H L L L
L X H H H
L X H H L
X X H L X
X X X X X
Illegal NOP (Idle after tRSC) NOP (Idle after tRSC) Illegal
READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL/REF/ SELF/MRS
L
L
X
X
X
Illegal
ABBREVIATIONS: RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge
Notes: *1. All entries in OPERATION COMMAND TABLE assume the CKE was High during the proceeding clock cycle and the current clock cycle. Illegal means don't used command. If used, power up sequence be asserted after power shut down. *2. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state of that bank. *3. Illegal if any bank is not idle. *4. Must satisfy bus contention, bus turn around, and/or write recovery requirements. Refer to "TIMING DIAGRAM -11 & -12" in section "s TIMING DIAGRAMS". *5. NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP). *6. SELF command should only be issued after the last read data have been appeared on DQ. *7. MRS command should only be issued on condition that all DQ are in Hi-Z.
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
COMMAND TRUTH TABLE FOR CKE Note *1
Current State Selfrefresh CKE n-1 H L CKE n X H CS X H RAS CAS X X X X WE X X Addr X X Invalid Exit Self-refresh (Self-refresh Recovery Idle after tRC) Exit Self-refresh (Self-refresh Recovery Idle after tRC) Illegal Illegal Illegal NOP (Maintain Self-refresh) Invalid Idle after tRC Idle after tRC Illegal Illegal Illegal Illegal Illegal *2 Function Notes
L L L L L Selfrefresh Recovery L H H H H H H H
H H H H L X H H H H H H L
L L L L X X H L L L L X X
H H H L X X X H H H L X X
H H L X X X X H H L X X X
H L X X X X X H L X X X X
X X X X X X X X X X X X X
(Continued)
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current State Power Down CKE n-1 H L L L L L All Banks Idle H CKE n X H H L H H H CS X H L X L L H RAS CAS X X H X L H X X X H X X L X WE X X H X X X X Addr X X X X X X MODE NOP (Maintain Power Down Mode) Illegal Illegal Refer to the Operation Command Table. Refer to the Operation Command Table. Refer to the Operation Command Table. Auto-refresh Refer to the Operation Command Table. Power Down Power Down Illegal Illegal Illegal Self-refresh Illegal Invalid *3 Invalid Exit Power Down Mode Idle Function Notes
H
H
L
H
X
X
MODE
H H H H H H H H H H L
H H H L L L L L L L X
L L L H L L L L L L X
L L L X H H H L L L X
H L L X H H L H L L X
X H L X H L X X H L X
MODE X MODE X X X X X X X X
(Continued)
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Current State Bank Active, Bank Activating, Read/Write CKE n-1 H CKE n H CS X RAS X CAS X WE X Addr X Function Notes
Refer to the Operation Command Table. Begin Clock Suspend next cycle Invalid Invalid Exit Clock Suspend next cycle Maintain Clock Suspend Invalid Refer to the Operation Command Table. Illegal
H L
L X X H L X H L
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
Clock Suspend
H L L
Any State Other Than Listed Above
L H H
Notes: *1. All entries in "COMMAND TRUTH TABLE FOR CKE" are specified at CKE(n) state and CKE input from CKE(n-1) to CKE(n) state must satisfy corresponding set up and hold time for CKE. *2. CKE should be held High for tRC period. *3. SELF command should only be issued after the last data have been appeared on DQ.
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM and conventional DRAMs are: synchronized operation, burst mode, and mode register. The synchronized operation is the fundamental difference. An SDRAM uses a clock input for the synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDRAM is determined by commands and all operations are referenced to a positive clock edge. Fig. 2 shows the basic timing diagram differences between SDRAMs and DRAMs. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column addresses for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to justify the SDRAM operation and function into desired system conditions. MODE REGISTER TABLE shows how SDRAM can be configured for system requirement by mode register programming.
CLOCK INPUT (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDRAM use register type buffers. A CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged), the Power Down mode (standby) is entered with CKE = Low and this will make extremely low standby current.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals are negated but internal operation such as burst cycle will not be suspended. If such a control isn't needed, CS can be tied to ground level.
COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operation, such as Row address strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge of the CLK determines SDRAM operation. Refer to "s FUNCTIONAL TRUTH TABLE".
ADDRESS INPUT (A0 to A10)
Address input selects an arbitrary location of a total of 524,288 words of each memory cell matrix. A total of nineteen address input signals are required to decode such a matrix. SDRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV), eleven Row addresses are initially latched and the remainder of eight Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or Write command (WRIT or WRITA).
BANK SELECT (BA0, BA1)
This SDRAM has four banks and each bank is organized as 512 K words by 32-bit. Bank selection by BA0, BA1 occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT or WRITA), and precharge command (PRE).
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
DATA INPUT AND OUTPUT (DQ0 to DQ31)
Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input: tRAC ; from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.) tCAC ; from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.) tAC ; from the clock edge after tRAC and tCAC. The polarity of the output data is identical to that of the input. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH).
DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and when DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. DQM0, DQM1, DQM2, DQM3, controls DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23, DQ24 to DQ31, respectively.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: Current Stage Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write Next Stage Burst Read 1st Step Burst Write 2nd Step Burst Write Burst Read Precharge Precharge Write Command after lOWD Write Command Read Command Precharge Command Precharge Command Method (Assert the following command) Read Command Mask Command (Normally 3 clock cycles)
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column address is even (0), the next address will be odd (1), or vice-versa.When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write operation. The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to the full column burst. The sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address (= 0).
17
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Burst Length 2
Starting Column Address A2 A1 A0 XX0 XX1 X00 X01 X10 X11 000 001 010 011 100 101 110 111
Sequential Mode 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Interleave 0-1 1-0 0-1-2- 3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
4
8
FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same column. If burst mode reaches end of column address, then it wraps round to first column address (= 0) and continues to count until interrupted by the news read (READ) /write (WRIT), precharge (PRE), or burst stop (BST) command. The selection of Auto-precharge option is illegal during the full column burst operation except write command at BURST READ & SINGLE WRITE mode. The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When read mode is interrupted by BST command, the output will be in High-Z. For the detail rule, please refer to "TIMING DIAGRAM - 8" in section "s TIMING DIAGRAMS". When write mode is interrupted by BST command, the data to be applied at the same time with BST command will be ignored.
BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this mode, burst read operation does not be affected by this mode.
18
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDRAM memory core is the same as conventional DRAMs', requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE). With the Precharge command, SDRAM will automatically be in standby state after precharge time (tRP). The precharged bank is selected by combination of AP and BA0, BA1 when Precharge command is asserted. If AP = High, all banks are precharged regardless of BA0, BA1 (PALL). If AP = Low, a bank to be selected by BA0, BA1 is precharged (PRE). The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command assertion. This auto precharge is entered by AP = High when a read or write command is asserted. Refer to "s FUNCTIONAL TRUTH TABLE".
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) generates Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 16 s or a total 4096 refresh commands within a 64 ms period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh function until cancelled by SELFX. The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF). Once SDRAM enters the self-refresh mode, all inputs except for CKE will be "don't care" (either logic high or low level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after last read data has been appeared on DQ Notes: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command (NOP) or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one tRC period after tCKSP. Refer to "TIMING DIAGRAM -16" in section "s TIMING DIAGRAMS" for the detail. It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period. Notes: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted after the self-refresh exit.
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation fields; Burst Length, Burst Type, CAS latency, and Operation Code. Refer to "s MODE REGISTER TABLE". The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power). MRS command should only be issued on condition that all DQ is in Hi-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of SDRAM. Refer to "POWER-UP INITIALIZATION" below.
19
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
POWER-UP INITIALIZATION
The SDRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. Apply power and start clock. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 s. 3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL). 4. Assert minimum of 2 Auto-refresh command (REF). 5. Program the mode register by Mode Register Set command (MRS). In addition, it is recommended DQM and CKE to track VCC to insure that output is High-Z state. The Mode Register Set command (MRS) can be set before 2 Auto-refresh command (REF).
20
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 2 - BASIC TIMING FOR CONVENTIONAL DRAM VS SYNCHRONOUS DRAM
Active CLK CKE H tSI CS tHI H H Read/Write Precharge
RAS
CAS H : Read WE L : Write Address BA RA BA CA CAS Latency = 2 BA AP (A10)
DQ0 to DQ31
Row Address Select RAS
Burst Length = 4
Column Address Select
Precharge
CAS DQ0 to DQ31
21
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 3 - STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
MRS MODE REGISTER SET IDLE
SELF SELFX SELF REFRESH REF CKE\(PD) CKE AUTO REFRESH POWER DOWN
CKE\(CSUS) BANK ACTIVE SUSPEND CKE BST WRIT WRIT WRITA WRITE SUSPEND CKE\(CSUS) WRITE CKE WRITA READA READ WRIT READA PRE or PALL WRITA READA READ CKE READ READ CKE\(CSUS) BANK ACTIVE BST
ACTV
READ SUSPEND
WRITE SUSPEND
CKE\(CSUS) WRITE WITH AUTO CKE PRECHARGE PRE or PALL
READ WITH AUTO PRECHARGE PRE or PALL
CKE\(CSUS) CKE READ SUSPEND
POWER ON
PRE or PALL
PRECHARGE
POWER APPLIED
DEFINITION OF ALLOWS Manual Input Automatic Sequence
Note: CKE\ means CKE goes Low-level from High-level.
22
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION
READA WRITA READ SELF
Second command (same bank) First command
*4 *4
ACTV
PALL
WRIT
MRS
PRE
REF
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRCD
tRCD
tRCD
*5
tRCD
*5
tRAS
*4
tRAS
*4
1
READ
*1,*2
1
1
1
1
1
*4
1
*4 *2 *2,*7
1
READA
BL + tRP
BL + tRP tWR
*2
BL + tRP
*4
BL + tRP
*4
BL + tRP
BL + tRP 1
WRIT
tWR
1
1
tDPL
*4
tDPL
*4 *2 *2
WRITA
BL-1 + tDAL
*2,*3
BL-1 + tDAL tRP
BL-1 + tDAL 1
BL-1 + tDAL
*4
BL-1 + tDAL
*2
BL-1 + tDAL
*2,*6
PRE
tRP
*3
1
tRP
tRP
*6
1
PALL
tRP
tRP
1
1
tRP
tRP
1
REF
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX
tRC
tRC
tRC
tRC
tRC
tRC
tRC
Notes: *1. If tRP(min.)*2. *3. *4. *5. *6. *7. Assume all banks are in Idle state. Assume output is in High-Z state. Assume tRAS(min.) is satisfied. Assume no I/O conflict. Assume after the last data have been appeared on DQ. If tRP(min.)<(CL-1)xtCK, minimum latency is a sum of (BL+CL-1)xtCK.
Illegal Command 23
BST
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s MULTI BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
READA READ WRITA ACTV PALL WRIT MRS SELF
Second command (other bank) First command
*5 *5,*6 *5 *5,*6
PRE
REF
MRS
tRSC
tRSC
*2 *7 *7 *7 *7
tRSC
*6,*7
tRSC
*7
tRSC
tRSC
tRSC
ACTV
tRRD
*2,*4
1
1
1
*10
1
*10
1
*6
tRAS
*6
READ
*1,*2
1
*2,*4
1
*6
1
*6
1
*6,*10
1
*6,*10
1
*6
1
*6 *2 *2,*9
READA
BL+ tRP
1
*2,*4
1
1
1
1
1
*6
BL+ tRP
*6
BL+ tRP
BL+ tRP 1
WRIT
*2
1
*2,*4
1
*6
1
*6
1
*6
1
*6
1
*6
tDPL
*6 *2 *2
WRITA
BL-1 + tDAL
*2,*3
1
*2,*4
1
*7
1
*7
1
*7
1
*7
1
*6,*7
BL-1 + tDAL
*7
BL-1 + tDAL
*2
BL-1 + tDAL
*2,*8
PRE
tRP
*3
1
1
1
1
1
1
1
tRP
tRP
*8
PALL
tRP
tRP
1
1
tRP
tRP
REF
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX Notes:
*1. *2. *3. *4. *5. *6. *7. *8. *9. *10.
tRC
tRC
tRC
tRC
tRC
tRC
tRC
If tRP(min.)Illegal Command
24
BST 1 1 1 1
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s MODE REGISTER TABLE
MODE REGISTER SET
BA1 0 BA0 0 A10 0 A9 Opcode A8
*3
A7
*3
A6
A5 CL
A4
A3 BT
A2
A1 BL
A0
ADDRESS MODE REGISTER
0
0
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 BT = 0 0 1 0 1 0 1 0 1 1 2 4 8 Reserved Reserved Reserved Full Column BT = 1
*2
Reserved 2 4 8 Reserved Reserved Reserved Reserved
A9 0 1
Op-code Burst Read & Burst Write Burst Read & Single Write
*1
A3 0 1
Burst Type Sequential (Wrap round, Binary-up) Interleave (Wrap round, Binary-up)
Notes: *1. When A9 = 1, burst length at Write is always one regardless of BL value. *2. BL = 1 and Full Column are not applicable to the interleave mode. *3. A7 = 1 and A8 = 1 are reserved for vender test.
25
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage of VCC Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Storage Temperature Symbol VCC, VCCQ VIN, VOUT IOUT PD TSTG Value -0.5 to +4.6 -0.5 to +4.6 50 1.3 -55 to +125 Unit V V mA W C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter Supply Voltage VSS, VSSQ Input High Voltage Input Low Voltage Ambient Temperature Notes:
4.6V 50% of pulse amplitude VIH VIH(min.) VIL Pulse width 5 ns VIH VIL(max.) VIL 50% of pulse amplitude -1.5V Pulse width 5 ns
Notes
Symbol VCC, VCCQ
Min. 3.0 0 2.0 -0.5 0
Typ. 3.3 0 -- -- --
Max. 3.6 0 VCC + 0.5 0.8 70
Unit V V V V C
*1 *2
VIH VIL TA
*1. Overshoot limit: VIH (max.) = 4.6V for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude.
*2. Undershoot limit: VIL (min.) = VSS -1.5V for pulse width <= 5 ns acceptable, pulse width measured at 50% of pulse amplitude.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
s CAPACITANCE
Parameter Input Capacitance, Except for CLK Input Capacitance for CLK I/O Capacitance 26 Symbol CIN1 CIN2 CI/O Min. 2.5 2.5 4.0 Typ. -- -- --
(TA = 25C, f = 1 MHz) Max. 5.0 4.0 6.5 Unit pF pF pF
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, *2, and 3*
Parameter Output High Voltage Output Low Voltage Input Leakage Current (Any Input) Output Leakage Current MB81F643242C-60 MB81F643242C-70 ICC1 MB81F643242C-10 Reference Value *4 @67MHz (CL=3) Symbol VOH(DC) VOL(DC) ILI ILO Condition IOH = -2 mA IOL = 2 mA 0 V VIN VCC; All other pins not under test = 0 V 0 V VIN VCC; Data out disabled Burst: Length = 1 tRC = min, tCK = min One bank active Output pin open Addresses changed up to 1-time during tRC (min) 0 V VIN VIL max VIH min VIN VCC CKE = VIL All banks idle tCK = min Power down mode 0 V VIN VIL max VIH min VIN VCC CKE = VIL All banks idle CLK = VIH or VIL Power down mode 0 V VIN VIL max VIH min VIN VCC CKE = VIH All banks idle, tCK = 15 ns NOP commands only, Input signals (except to CMD) are changed 1 time during 30 ns 0 V VIN VIL max VIH min VIN VCC CKE = VIH All banks idle CLK = VIH or VIL Input signal are stable 0 V VIN VIL max VIH min VIN VCC Value Min. Max. 2.4 -- -- 0.4 -5 -5 5 5 165 155 -- 115 100 mA Unit V V A A
Operating Current (Average Power Supply Current)
ICC2P
--
2
mA
ICC2PS
--
1
mA
Precharge Standby Current (Power Supply Current) ICC2N
--
12
mA
ICC2NS
--
2
mA
(Continued)
27
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
(Continued)
Parameter Symbol Condition CKE = VIL Any bank active tCK = min 0 V VIN VIL max VIH min VIN VCC CKE = VIL Any bank active CLK = VIH or VIL 0 V VIN VIL max VIH min VIN VCC CKE = VIH Any bank active tCK = 15 ns NOP commands only, Input signals (except to CMD) are changed 1 time during 30 ns 0 V VIN VIL max VIH min VIN VCC CKE = VIH Any bank idle CLK = VIH or VIL Input signals are stable 0 V VIN VIL max VIH min VIN VCC tCK = min Burst Length = 4 Output pin open All banks active Gapless data 0 V VIN VIL max VIH max VIN VCC Auto-refresh; tCK = min tRC = min 0 V VIN VIL max VIH max VIN VCC Self-refresh; tCK = min CKE 0.2 V 0 V VIN VIL max VIH max VIN VCC Value Min. Max. Unit
ICC3P
--
2
mA
ICC3PS
--
1
mA
Active Standby Current (Power Supply Current) ICC3N
--
25
mA
ICC3NS
--
2
mA
MB81F643242C-60 Burst mode Current (Average Power Supply Current) MB81F643242C-70 MB81F643242C-10 Reference Value *4 @67MHz (CL=3) MB81F643242C-60 Refresh Current #1 (Average Power Supply Current) MB81F643242C-70 MB81F643242C-10 Reference Value *4 @67MHz (CL=3) Refresh Current #2 (Average Power Supply Current) ICC5 ICC4
305 260 -- 185 125 235 220 -- 155 125 mA mA
ICC6
--
2
mA
Notes: *1. All voltage are referenced to VSS. *2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure in section "s FUNCTIONAL DESCRIPTION". *3. ICC depends on the output termination or load conditions, clock cycle rate, signal clocking rate. The specified values are obtained with the output open and no termination register. *4. This value is for reference only. 28
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1, 2, and *3
Parameter Notes CL = 2 Clock Period CL = 3 Clock High Time Clock Low Time Input Setup Time Input Hold Time Access Time from Clock (tCK = min) Output in Low-Z Output in High-Z Output Hold Time *5,*8 CL = 3 CL = 2 *5,*7 CL = 3 tREFI tREF tT tCKSP -- -- 0.5 1.5 15.6 64 10 -- -- -- 0.5 2 15.6 64 10 -- -- -- 0.5 3 15.6 64 10 -- -- -- 0.5 3 15.6 64 10 -- tOH 2.5 -- 2.5 -- 3 -- 3 -- ns s ms ns ns tHZ3 *5,*6, *7 *5 *5 *5 *5 CL = 2 CL = 3 *5 CL = 2 tCK3 tCH tCL tSI tHI tAC2 -- tAC3 tLZ tHZ2 2.5 5.5 1 5.5 -- 6 2.5 5.5 1 6 2.5 2.5 1.5 1 -- -- -- -- 6 -- 5.5 -- 6 3 7 1 Symbol tCK2
MB81F643242C MB81F643242C MB81F643242C Reference Value *4 -60 -70 -10 @67MHz, CL=3
Unit ns
Min. 10
Max. --
Min. 10
Max. --
Min. 15
Max. --
Min. 20
Max. --
7 2.5 2.5 2 1 -- -- -- -- 6
10 3 3 2 1 -- 7 -- 7 -- -- -- -- 7
15 4 4 3 1 -- 7 1 3 7 -- 7 -- -- -- -- 7
ns ns ns ns ns ns ns ns ns ns ns
Time between Auto-Refresh command interval *4 Time between Refresh Transition Time CKE Setup Time for Power Down Exit Time *5
29
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
BASE VALUES FOR CLOCK COUNT/LATENCY
Parameter Notes RAS Cycle Time Symbol
MB81F643242C -60 MB81F643242C MB81F643242C Reference Value *4 -70 -10 @67MHz, CL=3
Unit
Min. *9 tRC tRP tRAS tRCD tWR tRRD tDPL tDAL2 tDAL3 tRSC 60 18 42 18 6 12 7 1 cyc + tRP 2 cyc + tRP 12
Max. -- -- 110K -- -- -- -- -- -- --
Min. 63 20 42 20 7 14 7 1 cyc + tRP 2 cyc + tRP 14
Max. -- -- 110K -- -- -- -- -- -- --
Min. 90 30 60 30 10 20 10 1 cyc + tRP 2 cyc + tRP 20
Max. -- -- 110K -- -- -- -- -- -- --
Min. 110 40 70 30 15 30 15 1 cyc + tRP 2 cyc + tRP 30
Max. -- -- 110K -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns
RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to RAS Bank Active Delay Time Data-in to Precharge Lead Time Data-in to Active/ Refresh Command Period CL=2 CL=3
Mode Resister Set Cycle Time
CLOCK COUNT FORMULA
Clock
Note *10 (Round off a whole number)
Base Value Clock Period
30
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.) Parameter CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Outputing High-Z Delay Burst Stop Command to Output in High-Z Delay CAS to CAS Delay (min) CAS Bank Delay (min) CL = 2 CL = 3 CL = 2 CL = 3 Symbol lCKE lDQZ lDQD lOWD lDWD lROH2 lROH3 lBSH2 lBSH3 lCCD lCBD
MB81F643242C -60 MB81F643242C -70 MB81F643242C Unit -10
1 2 0 2 0 2 3 2 3 1 1
1 2 0 2 0 2 3 2 3 1 1
1 2 0 2 0 2 3 2 3 1 1
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure in section "s FUNCTIONAL DESCRIPTION". *2. AC characteristics assume tT = 1 ns and 30 pF of capacitive load. *3. 1.4 V is the reference level for measuring timing of input signals. Transition times are measured between VIH (min) and VIL (max). (See Fig. 5) *4. This value is for reference only. *5. If input signal transition time (tT) is longer than 1 ns; [(tT/2) -0.5] ns should be added to tAC (max), tHZ (max), and tCKSP (min) spec values, [(tT/2) -0.5] ns should be subtracted from tLZ (min), tHZ (min), and tOH (min) spec values, and (tT -1.0) ns should be added to tCH (min), tCL (min), tSI (min), and tHI (min) spec values. *6. tAC also specifies the access time at burst mode. *7. tAC and tOH are the specs value under OUTPUT LOAD CIRCUIT shown in Fig. 4. *8. Specified where output buffer is no longer driven. *9. Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP). *10. All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number).
31
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 4 - OUTPUT LOAD CIRCUIT
R1 = 50 Output 1.4 V
CL = 30 pF
LVTTL
Note: By adding appropriate correlation factors to the test conditions, tAC and tOH measured when the Output is coupled to
the Output Load Circuit are within specifications.
32
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 5 - TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME
tCK tCH
2.4 V
tCL
CLK
0.4 V
1.4 V
tSI Input (Control, Addr. & Data)
tHI
2.4 V 1.4 V 0.4 V
tAC tLZ tOH
tHZ
2.4 V
Output
0.4 V
1.4 V
Note: Reference level of input signal is 1.4 V for LVTTL. Access time is measured at 1.4 V for LVTTL.
Fig. 6 - TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT
CLK
Don't Care
tCKSP (min) CKE
1 clock (min)
Command
Don't Care
NOP
NOP
ACTV
33
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
Fig. 7 - TIMING DIAGRAM, PULSE WIDTH
CLK
Input (Control)
tRC, tRP, tRAS, tRCD, tWR, tREF, tDPL, tDAL, tRSC, tRRD, tCKSP
COMMAND COMMAND
Note: These parameters are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the latency value from the rising edge of CKE. Measurement reference voltage is 1.4 V.
Fig. 8 - TIMING DIAGRAM, ACCESS TIME
CLK
Command
READ
tAC (CAS Latency - 1) x tCK DQ0 to DQ31 (Output)
tAC
tAC
Q(Valid)
Q(Valid)
Q(Valid)
34
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s TIMING DIAGRAMS
TIMING DIAGRAM - 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE ICKE (1 clock) CLK (Internal)
*1
ICKE (1 clock)*1
*2 *2
DQ0 to DQ31 (Read)
Q1
Q2
(NO CHANGE)
*2
Q3
(NO CHANGE)
*2
Q4
DQ0 to DQ31 (Write)
D1
NOT *3 WRITTEN
D2
NOT *3 WRITTEN
D3
D4
Notes: *1. The latency of CKE (lCKE) is one clock. *2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output data remain the same data. *3. During the write mode, data at the next clock of CSUS command is ignored.
TIMING DIAGRAM - 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
CLK tCKSP
(min) 1 clock (min)
CKE
Command
NOP
*1
PD(NOP)
*2
DON'T CARE
NOP
*3
NOP
*3
ACTV
*4
tREF (max)
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2. Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ. *3. It is recommended to apply NOP command in conjunction with CKE. *4. The ACTV command can be latched after tCKSP (min) + 1 clock (min).
35
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS ICCD tRCD (min) CAS
(1 clock)
ICCD
ICCD
ICCD
Address
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
Note: CAS to CAS delay can be one or more clock period.
TIMING DIAGRAM - 4 : DIFFERENT BANK ADDRESS INPUT DELAY
CLK tRRD (min) RAS ICBD tRCD (min) or more CAS tRCD (min) Address
ROW ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS (1 clock)
ICBD
BA0, BA1
Bank 0
Bank 3
Bank 0
Bank 3
Bank 0
Bank 3
Note: CAS Bank delay can be one or more clock period.
36
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 5 : DQM0 - DQM3 - INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM0 to DQM3 (@ Read) IDQZ (2 clocks) DQ0 to DQ31 (@ Read)
Q1
Q2
Hi-Z
Q4
End of burst
DQM0 to DQM3 (@ Write) IDQD (same clock) DQ0 to DQ31 (@ Write)
D1
MASKED
D3
D4
End of burst
TIMING DIAGRAM - 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK tRAS (min) Command
ACTV
PRE
Note: PRECHARGE means ' PRE' or 'PALL'.
37
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
CLK
Command
PRECHARGE
IROH (2 clocks) DQ0 to DQ31
Q1 Hi-Z
Command
PRECHARGE
IROH (2 clocks) DQ0 to DQ31
Hi-Z
Q1
Q2
Command
PRECHARGE
IROH (2 clocks) DQ0 to DQ31
Hi-Z
Q1
Q2
Q3
Command
PRECHARGE No effect (end of burst)
DQ0 to DQ31
Q1
Q2
Q3
Q4
Note: In case of CL = 2, the lROH is 2 clocks. In case of CL = 3, the lROH is 3 clocks. PRECHARGE means ' PRE' or 'PALL'.
38
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL = Full Column)
CLK
Command (CL = 2)
BST
lBSH (2 clocks)
Hi-Z
DQ0 to DQ31
Qn-2
Qn-1
Qn
Qn+1
Command (CL = 3)
BST
lBSH (3 clocks)
Hi-Z Qn-2 Qn-1 Qn Qn+1 Qn+2
DQ0 to DQ31
TIMING DIAGRAM - 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ BL = 2)
CLK
Command
BST
COMMAND
DQ0 to DQ31
LAST DATA-IN
Masked by BST
39
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 10 : WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 3)
CLK
Command
PRECHARGE
ACTV
tDPL (min)
tRP (min)
DQ0 to DQ31
DATA-
LAST DATA-IN
MASKED by Precharge
Note: The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied. PRECHARGE means ' PRE' or 'PALL'.
TIMING DIAGRAM - 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 3, BL = 4)
CLK IOWD (2 clocks) Command
READ
WRIT
DQM (DQM0 to DQM3)
*1
*2
*3
IDQZ (2 clocks)
IDWD (same clock)
D1 Masked D2
DQ0 to DQ31
Q1
Notes: *1. First DQM makes high-impedance state High-Z between last output and first input data. *2. Second DQM makes internal output data mask to avoid bus contention. *3. Third DQM in illustrated above also makes internal output data mask. If burst read ends (final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention.
40
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
CLK tWR (min) Command
WRIT READ
DQM (DQM0 to DQM3) (CL-1) x tCK DQ0 to DQ31
D1 D2 D3 Masked by READ
tAC (max)
Q1 Q2
Note: Read command should be issued after tWR of final data input is satisfied.
41
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 13 : READ WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
CLK tRAS (min) tRP (min)
Command
ACTV
READA 2 clocks *1 (same value as BL)
NOP or DESL
ACTV
BL+tRP (min) *2
DQM (DQM0 to DQM3)
DQ0 to DQ31
Q1
Q2
Notes: *1. Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as Burst Length (BL) after the READA command is asserted. *2. Next ACTV command should be issued after BL+tRP (min) from READA command.
TIMING DIAGRAM - 14 : WRITE WITH AUTO-PRECHARGE *1, *2, and *3 (EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
tRAS (min)
CLK CL- 1
*4
tDAL (min) BL+tRP (min) *5
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM (DQM0 to DQM3)
DQ0 to DQ31
D1
D2
Notes: *1. Even if the final data is masked by DQM, the precharge does not start the clock of final data input. *2. Once auto precharge command is asserted, no new command within the same bank can be issued. *3. Auto-precharge command doesn't affect at full column burst operation except Burst READ & Single Write. *4. Precharge at write with Auto-precharge is started after the CL - 1 from the end of burst. *5. Next command should be issued after BL+ tRP (min) at CL = 2, BL+1+tRP (min) at CL = 3 from WRITA command.
42
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 15 : AUTO-REFRESH TIMING
CLK
Command
REF *1
NOP *3
NOP *3
NOP *3
REF
NOP *3
Command *4
tRC (min)
*2 *2
tRC (min)
DON'T CARE BA
BA0, BA1
DON'T CARE
Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF). *2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter. *3. Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode. *4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the last REF command.
TIMING DIAGRAM - 16 : SELF-REFRESH ENTRY AND EXIT TIMING
CLK tCKSP (min) tSI (min) CKE tRC (min) *4
Command
NOP *1
SELF
DON'T CARE
NOP
*2
SELFX
NOP
*3
Command
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF). *2. The Self-refresh Exit command (SELFX) is latched after tCKSP (min). It is recommended to apply NOP command in conjunction with CKE. *3. Either NOP or DESL command can be used during tRC period. *4. CKE should be held high within one tRC period after tCKSP.
43
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 17 : MODE REGISTER SET TIMING
CLK tRSC (min)
Command
MRS
NOP or DESL
ACTV
Address
MODE
ROW ADDRESS
Notes: The Mode Register Set command (MRS) should only be asserted after all banks have been precharged.
44
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s SCITT TEST MODE
ABOUT SCITT
SCITT (Static Component Interconnection Test Technology) is an XNOR circuit based test technology that is used for testing interconnection between SDRAM and SDRAM controller on the printed circuit boards. SCITT provides inexpensive board level test mode in combination with boundary-scan. The basic idea is simple, consider all output of SDRAM as output of XNOR circuit and each output pin has a unique mapping on the input of SDRAM. The ideal schematic block diagram is as shown below.
SDRAM Controller
C
Boundary Scan
TEST Control
xAddress Bus
SDRAM CORE XNOR
ASIC
Data Bus
TEST Control : CAS, CS, CKE xAddress Bus : A0 to A10, BA0, BA1, RAS, DQM0 to DQM3, CLK, WE Data Bus : DQ0 to DQ31
It is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short faults. The MB81F643242C adopts SCITT as an optional function. See Package and "Ordering Information" in section "s PACKAGE".
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MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge command in POWER-UP INITIALIZATION. Once Precharge command is issued to SDRAM, it never get back to SCITT Test Mode during regular operation for the purpose of a fail-safe way in get in and out of test mode. 1. Apply power. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power for a minimum of 100us. 3. Enter SCITT test mode. 4. Execute SCITT test. 5. Exit from SCITT mode. It is required to follow Power On Sequence to execute read or write operation. 6. Start clock. Attempt to maintain either NOP or DESL command at the input. 7. Precharge all banks by Precharge (PRE) or Precharge All command (PALL). 8. Assert minimum of 2 Auto-Refresh command (REF). 9. Program the mode register by Mode Register Set command (MRS). The 3,4,5 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to POWERUP INITIALIZATION).
COMMAND TRUTH TABLE Note *1
Control CAS SCITT mode entry SCITT mode exit SCITT mode output enable *4 HL *2 LH * L
3
Input CKE L L
*5
Output DQM0 to DQM3 X X V CLK X X V DQ0 to DQ31 X X V
CS L H
*5
WE X X V
RAS X X V
A0 to A10 BA0, BA1 X X V
L
H
Notes: *1. L = Logic Low, H = Logic High, V = Valid, X = either L or H *2. The SCITT mode entry command assumes the first CAS falling edge with CS and CKE = L after power on. *3. The SCITT mode exit command assumes the first CAS rising edge after the test mode entry. *4. Refer the test code table. *5. CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
46
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TEST CODE TABLE
DQ0 to DQ31 output data is static and is determined by following logic during the SCITT mode operation.
DQ0 = RAS xnor A0 DQ1 = RAS xnor A1 DQ2 = RAS xnor A2 DQ3 = RAS xnor A3 DQ4 = RAS xnor A4 DQ5 = RAS xnor A5 DQ6 = RAS xnor A6 DQ7 = RAS xnor A7 DQ8 = RAS xnor A8 DQ9 = RAS xnor A9 DQ10 = RAS xnor A10 DQ11 = RAS xnor BA1 DQ12 = RAS xnor BA0 DQ13 = RAS xnor DQM0 DQ14 = RAS xnor DQM1 DQ15 = RAS xnor DQM2 DQ16 = RAS xnor DQM3 DQ17 = RAS xnor CLK DQ18 = RAS xnor WE DQ19 = A0 xnor A1 DQ20 = A0 xnor A2 DQ21 = A0 xnor A3 DQ22 = A0 xnor A4 DQ23 = A0 xnor A5 DQ24 = A0 xnor A6 DQ25 = A0 xnor A7 DQ26 = A0 xnor A8 DQ27 = A0 xnor A9 DQ28 = A0 xnor A10 DQ29 = A0 xnor BA1 DQ30 = A0 xnor BA0 DQ31 = A0 xnor DQM0
* EXAMPLE OF TEST CODE TABLE
Input bus Output bus RAS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA1 BA0 DQM0 DQM1 DQM2 DQM3 CLK WE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 HHHHHHHHHHHHHHHHHHHH 00000LLLLLLLLLLLLLLLLLLLH 0 0 0 0 0 L HHHHHHHHHHHHHHHHHHL 0 0 0 0 0 HL HHHHHHHHHHHHHHHHHL 0 0 0 0 0 HHL HHHHHHHHHHHHHHHHH 0 0 0 0 0 HHHL HHHHHHHHHHHHHHHH 0 0 0 0 0 HHHHL HHHHHHHHHHHHHHH 0 0 0 0 0 HHHHHL HHHHHHHHHHHHHH 0 0 0 0 0 HHHHHHL HHHHHHHHHHHHH 0 0 0 0 0 HHHHHHHL HHHHHHHHHHHH 0 0 0 0 0 HHHHHHHHL HHHHHHHHHHH 0 0 0 0 0 HHHHHHHHHL HHHHHHHHHH 0 0 0 0 0 HHHHHHHHHHL HHHHHHHHH 0 0 0 0 0 HHHHHHHHHHHL HHHHHHHH 0 0 0 0 0 HHHHHHHHHHHHL HHHHHHH 0 0 0 0 0 HHHHHHHHHHHHHL HHHHHH 1 0 0 0 0 HHHHHHHHHHHHHHL HHHHH 0 1 0 0 0 HHHHHHHHHHHHHHHL HHHH 0 0 1 0 0 HHHHHHHHHHHHHHHHL HHH 0 0 0 1 0 HHHHHHHHHHHHHHHHHL HH 0 0 0 0 1 HHHHHHHHHHHHHHHHHHL H 11111LLLLLLLLLLLLLLLLLLLH 1 1 1 1 1 L HHHHHHHHHHHHHHHHHHL 1 1 1 1 1 HL HHHHHHHHHHHHHHHHHL 1 1 1 1 1 HHL HHHHHHHHHHHHHHHHH 1 1 1 1 1 HHHL HHHHHHHHHHHHHHHH 1 1 1 1 1 HHHHL HHHHHHHHHHHHHHH 1 1 1 1 1 HHHHHL HHHHHHHHHHHHHH 1 1 1 1 1 HHHHHHL HHHHHHHHHHHHH 1 1 1 1 1 HHHHHHHL HHHHHHHHHHHH 1 1 1 1 1 HHHHHHHHL HHHHHHHHHHH 1 1 1 1 1 HHHHHHHHHL HHHHHHHHHH 1 1 1 1 1 HHHHHHHHHHL HHHHHHHHH 1 1 1 1 1 HHHHHHHHHHHL HHHHHHHH 1 1 1 1 1 HHHHHHHHHHHHL HHHHHHH 1 1 1 1 1 HHHHHHHHHHHHHL HHHHHH 0 1 1 1 1 HHHHHHHHHHHHHHL HHHHH 1 0 1 1 1 HHHHHHHHHHHHHHHL HHHH 1 1 0 1 1 HHHHHHHHHHHHHHHHL HHH 1 1 1 0 1 HHHHHHHHHHHHHHHHHL HH 1 1 1 1 0 HHHHHHHHHHHHHHHHHHL H 1 1 1 1 1 HHHHHHHHHHHHHHHHHHHH 0 = input Low, 1 = input High, L = output Low, H = output High H H L H L H H H H H H H H H H H H H H H H H L H L H H H H H H H H H H H H H H H H H H H L H H L H H H H H H H H H H H H H H H H L H H L H H H H H H H H H H H H H H H H H H L H H H L H H H H H H H H H H H H H H H L H H H L H H H H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H L H H H H L H H H H H H H H H H H H H H H H L H H H H H L H H H H H H H H H H H H H L H H H H H L H H H H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H L H H H H H H H H H H H L H H H H H H H H H L H H H H H H H H H H H H L H H H H H H L H H H H H H H H H H H H L H H H H H H
47
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
AC SPECIFICATION
Parameter tTS tTH tEPD tTLZ tTHZ tTCA tTIA tTOH tETD tTIH Description Test mode entry set up time Test mode entry hold time Test mode exit to power on sequence delay time Test mode output in Low-Z time Test mode output in High-Z time Test mode access time from control signals (output enable & chip select) Test mode Input access time Test mode Output Hold time Test mode entry to test delay time Test mode input hold time Minimum 10 10 10 0 0 -- -- 0 10 30 Maximum -- -- -- -- 20 40 20 -- -- -- Units ns ns ns ns ns ns ns ns ns ns
TIMING DIAGRAMS
TIMING DIAGRAM - 1 : POWER-UP TIMING DIAGRAM
*2 VDD 100s Pause Time Test Mode Entry Point CS
CKE
CAS
*3
*1
Notes: *1. SCITT is enabled if CS = L, CKE = L, CAS = L at just power on. *2. All output buffers maintains in High-Z state regardless of the state of control signals as long as the above timing is maintained. *3. CAS must not be brought from High to Low.
48
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence and normal operation VCC Pause 100s tTS tTH Test Mode tEPD
CAS
HL
CS
L
CKE
L *3 *2 Entry
*2. PRE or PALL commands must not be asserted. Test mode is disable by those commands. *3. Outputs must be disabled by CS = H or CKE = L before Exit.
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, CKE pins will have some problems.
49
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 3 : OUTPUT CONTROL (1)
VDD
Entry CAS must not brought from High to Low
CAS DQ turn to Low-Z at CS=L and CKE=H CS DQ turn to High-Z at CS=H
CKE High-Z DQ0 to DQ31 Memory device output buffer status High-Z Time (a) This is not bus line level tTLZ Low-Z Time (b) tTHZ High-Z Time (c)
TIMING DIAGRAM - 4 : OUTPUT CONTROL (2)
VDD
Entry CAS must not brought from High to Low
CAS DQ turn to Low-Z at CS=L and CKE=H CS DQ turn to High-Z at CKE=L CKE High-Z DQ0 to DQ31 Memory device output buffer status High-Z Time (a) This is not bus line level tTLZ Low-Z Time (b) tTHZ High-Z Time (c)
50
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 5 : TEST TIMING (1)
Test mode Entry Command tETD CAS Test mode Entry Under test
CS CKE
DQ becomes Low-Z at CS=L and CKE=H
A0 tTCA Under Check Pins A1 tTIA A2 tTOH DQ0 to DQ31 Valid tTOH Valid Valid tTIA tTIA
tTLZ
51
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 6 : TEST TIMING (2)
Test mode Entry CAS L Test mode Exit
Under test
CS-#1
L H Changed under test devices Tested #1 device Tested #2 device
CS-#2
CKE tTIH tTIH tTIH tTCA tTLZ Under Check Pins tTHZ A1 tTIA A2 tTOH DQ0 to DQ31 Valid tTOH Valid Valid tTOH Valid Valid tTIA tTIA tTIA tTIA
A0
52
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
TIMING DIAGRAM - 7 : TEST TIMING (3)
Test mode Entry CAS L Test mode Exit
Under test
CS-#1
L H Changed under test devices Tested #1 device Tested #2 device
CS-#2
CKE tTIH tTIH tTHZ tTIH
A0 tTCA A1 tTIA A2 tTOH DQ0 to DQ31 Valid tTOH Valid Valid tTOH Valid Valid tTIA tTIA tTLZ tTIA tTIA
Under Check Pins
53
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
s PACKAGE DIMENSION
86-pin plastic TSOP(II) (FPT-86P-M01)
86 44
*: Resin protrusion. (Each side: 0.15 (.006) MAX)
Details of "A" part
0.25(.010)
INDEX 0~8 0.45/0.75 (.018/.030)
LEAD No.
1
43
* 22.220.10(.875.004) 0.22 .009
+0.05 -0.04 +.002 -.002
11.760.20(.463.008) 1.20(.047)MAX
(Mounting height)
0.10(.004)
M
10.160.10(.400.004)
0.145 -0.03 +.002 .006 -.001
+0.05
0.50(.020)TYP
0.10(.004) 21.00(.827)REF
0.100.05 (.004.002) (STAND OFF)
"A"
C
1996 FUJITSU LIMITED F86001S-1C-1
Dimensions in MM (inches)
54
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
MEMO
55
MB81F643242C-60/-70/-10 Advanced Info (AE0.1E)
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inhereut chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F0001 (c) FUJITSU LIMITED Printed in Japan
56

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